Temperature sensors in SOI CMOS for high temperature applications

Ph.DDOCTOR OF PHILOSOPH

On‐Chip Lifetime Prediction for Dependable Many‐Processor SoCs based on Data Fusion

The developments in technology and complexity of many-processor Systems-on-Chips emerge at a very rapid pace as is their introduction in safety-critical applications, for instance the transport sector. The inherent decrease in dependability of these complex nanosystems must be compensated by counter measures. One promising approach is the usage of IJTAG-compatible embedded instruments in and around cores, monitoring the "health" of target processors. It has been anticipated that these instruments will be (primarily) used for reducing the cost of final testing. In case of degradation during life time, however, they can be reused and counteractions like run-time remapping can be carried out. In this paper, the on-line data of two types of embedded instruments will be used for the prognostics, a slack-delay monitor and an IDDX monitor. Their (correlated) data is being fused which enables a more accurate life-time prediction as compared to a single monitor approach. However, the computational requirements for the embedded dependability manager will increase to enable handling embedded instrument data fusion and/or multi-parameter life-time prediction

IJTAG Compatible Delay-line based Voltage Embedded Instrument with One Clock-cycle Conversion Time

The monitoring of critical-paths in Systems-on-Chip to ensure dependable operation during the lifetime is becoming essential for safety-critical applications. Based on the timing information, different procedures like remaining lifetime prediction, voltage, and frequency scaling can be carried out to retain the desired functionality. To perform these operations, it is important to measure the run-time changing parameters like operating voltage and temperature, at the same moment of measuring slack-delay timing in critical paths. This will provide a better correlation, as compared to measuring the slack-delay timing alone, for instance, to determine the remaining lifetime. This paper presents a novel delay-line based voltage embedded instrument with a conversion time of just one clock cycle along with its integration to the IJTAG network. The proposed embedded instrument (EI) has been designed using the TSMC 40nm standard cell library. Simulation results of the proposed EI show a resolution of 10mV with a detection range from 0.95V to 1.20V, which is sufficient for most dependability applications

IJTAG compatible analogue embedded instruments for MPSoC life-time prediction

Decreasing reliability of nanometer CMOS technologies with each technology generation is a bottleneck for development of dependable Cyber Physical Systems. This paper presents two analogue health monitors, namely IDDT and temperature along with their integration to the IJTAG network for MPSoC life-time prediction. The monitors are integrated as embedded instruments in a MPSoC. A technique for dynamic synthesis of the analogue front-end for the IDDT instrument and an architecture for integrating analogue embedded instruments into an IJTAG network is introduced in this paper. The embedded instruments have been designed in TSMC 40nm CMOS technology

Enhancing Physical Unclonable Function Robustness Employing Embedded Instruments

This paper proposes a methodology to improve the robustness of CMOS physical unclonable functions with regard to environmental parameter variations and thus enhancing the security. The methodology exploits the reuse of embedded instruments which are being deployed for dependability purposes. The approach is hardware and power efficient which is especially important for applications such as IoT. Chip implementation of the embedded instruments in 40nm CMOS technology is presented in addition to simulations and experimental validation on an FPGA

Design and Implementation of a Dependable CPSoC for Automotive Applications

Safety-critical cyber-physical systems-on-chip, consisting of analog/mixed-signal front- and back-ends combined with massive digital many-processor cores, are being increasingly applied. The imminent collision detection chip for cars is an example of this and such a complex system requires zero downtime and a very high dependability. By on-line monitoring the health status of processor cores and IPs and taking counteractions, we have accomplished this goal via IJTAG-compatible embedded instruments and appropriate embedded software. An IJTAG-compatible Iddt monitor has been designed, a slack-delay embedded instrument for detecting timing issues, as well as a monitor for detecting intermitted resistive faults in interconnections. By the on-chip replacement of degraded (non-healthy) cores, the lifetime can be increased by a factor of around four of our mixed-signal cyber-physical systems-on-chip

A time-domain band-gap temperature sensor in SOI CMOS for higherature applications

10.1109/TCSII.2014.2386231IEEE Transactions on Circuits and Systems II: Express Briefs625436-44

Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems

In safety-critical cyber-physical systems, analog front-ends combined with many-processors are being increasingly employed. An example is an imminent collision detection chip for cars. Such a complex system requires zero downtime and a very high dependability despite aging issues under harsh environmental conditions. By on-line monitoring the health status of the processor cores and taking appropriate counteractions if required, we have accomplished this goal in the past via IJTAG compatible embedded instruments and appropriate embedded software. This paper extends this approach to the analog / mixed-signal frontends of these systems, thereby creating a new uniform approach in design & test methodology, as well as a streamlined fault management. An IJTAG-compatible voltage monitor is introduced, for measuring aging-generated offset in OpAmps and SAR ADCs, as well as a delay-monitoring embedded instrument for detecting timing issues in ADCs. In addition, two-stage counter measures, like digitized recalibration and subsequent replacement, are presented to increase the lifetime by factors of the analog front-end of Cyber-Physical Systems-on-Chips